?002 fairchild semiconductor corporation rft2p03l rev. b rft2p03l 2.1a, 30v, 0.150 ohm, p-channel logic level, power mosfet this product is a p-channel power mosfet manufactured using the megafet process. this process, which uses feature sizes approaching those of lsi circuits, gives optimum utilization of silicon, resulting in outstanding performance. it was designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. this transistor can be operated directly from integrated circuits. formerly developmental type ta49222. features 2.1a, 30v ? ds(on) = 0.150 ? temperature compensating pspice model thermal impedance spice model peak current vs pulse width curve uis rating curve related literature - tb334, ?uidelines for soldering surface mount components to pc boards symbol packaging sot-223 ordering information part number package brand rft2p03l sot-223 2p03l note: rft2p03l is available only in tape and reel. use the entire part number and add the suf? t. d g s drain source gate drain (flange) january 2002 data sheet
?002 fairchild semiconductor corporation rft2p03l rev. b absolute maximum ratings t a = 25 o c, unless otherwise speci?d units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss -30 v drain to gate voltage (r gs = 20k ? ) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dgr -30 v gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v gs 20v v drain current continuous (note 2) (figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i d pulsed drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i dm 2.1 figure 5 a pulsed avalanche rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as figures 6, 14, 15 power dissipation (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d derate above 25 o c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 0.009 w w/ o c operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 150 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 125 o c. electrical speci?ations t a = 25 o c, unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 11) -30 - - v gate to source threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 10) -1 - -3 v zero gate voltage drain current i dss v ds = -30v, v gs = 0v - - -1 a v ds = -30v, v gs = 0v, t a = 150 o c - - -50 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance r ds(on) i d = 2.1a, v gs = -10v (figure 9) - 0.120 0.150 ? i d = 2.1a, v gs = -4.5v (figure 9) - 0.300 0.360 ? turn-on time t on v dd = -15v, i d ? 2.1a, r l = 7.1 ? , v gs = ? 10v, r gs = 21 ? - - 50 ns turn-on delay time t d(on) -13 - ns rise time t r -18 - ns turn-off delay time t d(off) -43 - ns fall time t f -24 - ns turn-off time t off - - 100 ns total gate charge q g(tot) v gs = 0v to -20v v dd = -15v, i d ? 2.1a, r l = 7.1 ? i g(ref) = -1.0ma (figure 13) -2733nc gate charge at -10v q g(-10) v gs = 0v to -10v - 14 17 nc threshold gate charge q g(th) v gs = 0v to -2v - 1.3 1.6 nc input capacitance c iss v ds = -25v, v gs = 0v, f = 1mhz (figure 12) - 620 - pf output capacitance c oss - 240 - pf reverse transfer capacitance c rss -30 - pf thermal resistance junction to ambient r ja pad area = 0.171 in 2 (see note 2) - - 110 o c/w pad area = 0.068 in 2 (see tech brief 377) - - 128 o c/w pad area = 0.026 in 2 (see tech brief 377) - - 147 o c/w source to drain diode speci?ations parameter symbol test conditions min typ max units source to drain diode voltage v sd i sd = -2.1a - - -1.25 v reverse recovery time t rr i sd = -2.1a, di sd /dt = 100a/ s--49ns reverse recovered charge q rr i sd = -2.1a, di sd /dt = 100a/ s--45nc note: 2. 110 o c/w measured using fr-4 board with 0.171 in 2 footprint for 1000 seconds. rft2p03l
?002 fairchild semiconductor corporation rft2p03l rev. b typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs ambient temperature figure 2. maximum continuous drain current vs ambient temperature figure 3. normalized maximum transient thermal impedance figure 4. forward bias safe operating area figure 5. peak current capability t a , ambient temperature ( o c) power dissipation multiplier 0 0 25 50 75 100 150 0.2 0.4 0.6 0.8 1.0 1.2 125 0 -0.5 -1.0 -1.5 -2.0 -2.5 25 50 75 100 125 150 i d , drain current (a) t a , ambient temperature ( o c) r ja = 110 o c/w 0.01 0.1 1 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 2 z ja , normalized thermal impedance single pulse notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t a p dm t 1 t 2 duty cycle - descending order 0.5 0.2 0.1 0.05 0.01 0.02 t, rectangular pulse duration (s) 0.001 r ja = 110 o c/w -0.1 -1 -10 -100 -1 -10 -100 v ds , drain to source voltage (v) i d , drain current (a) t j = max rated t a = 25 o c 100 s 10ms 1ms r ja = 110 o c/w limited by r ds(on) area may be operation in this -1 -10 -30 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 t, pulse width (s) i dm , peak current (a) i = i 25 150 - t a 125 for temperatures above 25 o c derate peak current as follows: r ja = 110 o c/w t a = 25 o c rft2p03l
?002 fairchild semiconductor corporation rft2p03l rev. b note: refer to fairchild application notes an9321 and an9322. figure 6. unclamped inductive switching capability figure 7. saturation characteristics figure 8. transfer characteristics figure 9. normalized drain to source on resistance vs junction temperature figure 10. normalized gate threshold voltage vs junction temperature figure 11. normalized drain to source breakdown voltage vs junction temperature typical performance curves unless otherwise speci?d (continued) i as , avalanche current (a) t av , time in avalanche (ms) starting t j = 25 o c starting t j = 150 o c t av = (l)(i as )/(1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1] -1 -6 1 10 100 -2 -3 -4 -5 0 -4 -8 -12 -16 -20 0 -1.5 -3.0 -4.5 -6.0 -7.5 i d , drain current (a) v ds , drain to source voltage (v) pulse duration = 250 s t a = 25 o c v gs = -4.5v v gs = -5v v gs = -6v v gs = -20v v gs = -10v v gs = -7v duty cycle = 0.5% max 0 -4 -8 -12 -16 -20 0 -1.5 -3.0 -4.5 -6.0 -7.5 i d, drain current (a) v gs , gate to source voltage (v) pulse duration = 250 s duty cycle = 0.5% max v dd = 15v 25 o c -55 o c 150 o c 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -80 -40 0 40 80 120 160 normalized drain to source t j , junction temperature ( o c) on resistance pulse duration = 80 s v gs = -10v, i d = 2.1a duty cycle = 0.5% max 0.6 0.8 1.0 1.2 -80 -40 0 40 80 120 160 normalized gate t j , junction temperature ( o c) threshold voltage v gs = v ds , i d = 250 a 0.9 1.0 1.1 1.2 -80 -40 0 40 80 120 160 breakdown voltage t j , junction temperature ( o c) normalized drain to source i d = 250 a rft2p03l
?002 fairchild semiconductor corporation rft2p03l rev. b figure 12. capacitance vs drain to source voltage note: refer to fairchild application notes an7254 and an7260. figure 13. gate charge waveforms for constant gate current test circuits and waveforms figure 14. unclamped energy test circuit figure 15. unclamped energy waveforms figure 16. gate charge test circuit figure 17. gate charge waveform typical performance curves unless otherwise speci?d (continued) 0 150 300 450 600 750 0 -5 -10 -15 -20 -25 -30 c, capacitance (pf) v ds , drain to source voltage (v) c iss c oss c rss v gs = 0v, f = 0.1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gd 0 -2 -4 -6 -8 -10 03691215 v gs , gate to source voltage (v) v dd = -15v q g , gate charge (nc) i d = 2.1a i d = 1a waveforms in descending order: t p 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v gs v dd v ds bv dss t p i as t av 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = -2v q g(-10) v gs = -10v q g(tot) v gs = -20v v ds -v gs i g(ref) 0 0 rft2p03l
?002 fairchild semiconductor corporation rft2p03l rev. b thermal resistance vs. mounting pad area the maximum rated junction temperature, t jm , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, p dm , in an application. therefore the application s ambient temperature, t a ( o c), and thermal impedance r ja ( o c/w) must be reviewed to ensure that t jm is never exceeded. equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. in using surface mount devices such as the sot-223 package, the environment in which it is applied will have a signi?ant in?ence on the part s current and maximum power dissipation ratings. precise determination of the p dm is complex and in?enced by many factors: 1. mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board 2. the number of copper layers and the thickness of the board 3. the use of external heat sinks 4. the use of thermal vias 5. air ?w and board orientation 6. for non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. fairchild provides thermal information to assist the designer s preliminary application evaluation. figure 20 de?es the r ja for the device as a function of the top copper (component side) area. this is for a horizontally positioned fr-4 board with 1oz copper after 1000 seconds of steady state power with no air ?w. this graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. pulse applications can be evaluated using the fairchild device spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. displayed on the curve are r ja values listed in the electrical speci?ations table. the points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, p dm . thermal resistances corresponding to other component side copper areas can be obtained from figure 20 or by calculation using equation 2. the area, in square inches is the top copper area including the gate and source pads. figure 18. switching time test circuit figure 19. resistive switching waveforms test circuits and waveforms (continued) v gs r l r gs dut + - v dd v ds v gs t d(on) t r 90% 10% v ds 90% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on 10% 0 0 (eq. 1) p dm t jm t a () r ja ------------------------------ - = 50 100 150 200 0.01 0.1 1.0 147 o c/w - 0.026in 2 area, top copper area (in 2 ) r ja ( o c/w) 128 o c/w - 0.068in 2 110 o c/w - 0.171in 2 r ja = 75.9 - 19.3 * in (area) figure 20. thermal resistance vs mounting pad area (eq. 2) r ja 75.9 19.3 in area () = rft2p03l
?002 fairchild semiconductor corporation rft2p03l rev. b pspice electrical model .subckt rft2p03l 2 1 3 ; rev july 1998 ca 12 8 6.5e-10 cb 15 14 6.4e-10 cin 6 8 5.77e-10 dbody 5 7 dbodymod dbreak 7 11 dbreakmod dplcap 10 6 dplcapmod ebreak 5 11 17 18 -41.2 eds 14 8 5 8 1 egs 13 8 6 8 1 esg 5 10 8 6 1 evthres 6 21 19 8 1 evtemp 6 20 18 22 1 it 8 17 1 ldrain 2 5 1e-9 lgate 1 9 1.27e-9 lsource 3 7 4.2e-10 mmed 16 6 8 8 mmedmod mstro 16 6 8 8 mstromod mweak 16 21 8 8 mweakmod rbreak 17 18 rbreakmod 1 rdrain 50 16 rdrainmod 24e-3 rgate 9 20 5.2 rldrain 2 5 10 rlgate 1 9 12.7 rlsource 3 7 4.2 rslc1 5 51 rslcmod 1e-6 rslc2 5 50 1e3 rsource 8 7 rsourcemod 68e-3 rvthres 22 8 rvthresmod 1 rvtemp 18 19 rvtempmod 1 s1a 6 12 13 8 s1amod s1b 13 12 13 8 s1bmod s2a 6 15 14 13 s2amod s2b 13 15 14 13 s2bmod vbat 22 19 dc 1 eslc 51 50 value={(v(5,51)/abs(v(5,51)))*(pwr(v(5,51)/(1e-6*45),2.5))} .model dbodymod d (is = 2e-13 rs = 3.5e-2 ikf = 0.7 xti = 8.2 trs1 = 6e-4 trs2 = 5e-7 cjo = 7.3e-10 tt = 3.51e-8 m = 0.4 .model dbreakmod d (rs = 2e-1 trs1 = 1e-4 trs2 = 1e-5) .model dplcapmod d (cjo = 2.65e-10 is = 1e-30 n = 10 m = 0.63) .model mmedmod pmos (vto = -2.6 kp = 1.2 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 5.2) .model mstromod pmos (vto = -3.27 kp = 6 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u) .model mweakmod pmos (vto = -2.11 kp = 0.07 is = 1e-30 n = 10 tox = 1 l = 1u w = 1u rg = 52 rs = 0.1) .model rbreakmod res (tc1 = 9.2e-4 tc2 = -1e-7) .model rdrainmod res (tc1 = 1.8e-2 tc2 = 2.1e-5) .model rslcmod res (tc1 = 3.5e-3 tc2 = 1.3e-6) .model rsourcemod res (tc1 = 0 tc2 = 0) .model rvthresmod res (tc1 = 8.8e-4 tc2 = 6.1e-6) .model rvtempmod res (tc1 = -2e-3 tc2 = 1e-6) .model s1amod vswitch (ron = 1e-5 roff = 0.1 von = 5.7 voff= 2.7) .model s1bmod vswitch (ron = 1e-5 roff = 0.1 von = 2.7 voff= 5.7) .model s2amod vswitch (ron = 1e-5 roff = 0.1 von = -0.1 voff= -2.4) .model s2bmod vswitch (ron = 1e-5 roff = 0.1 von = -2.4 voff= -0.1) .ends note: for further discussion of the pspice model, consult a new pspice sub-circuit for the power mosfet featuring global temperature options ; ieee power electronics specialist conference records, 1991, written by william j. hepp and c. frank wheatley. 1 gate rgate evtemp 18 22 9 + 12 13 8 14 13 13 15 s1a s1b s2a s2b ca cb egs eds cin mweak rdrain dbreak ebreak dbody drain rsource source rbreak rvtemp vbat it evthres esg dplcap eslc rslc1 rslc2 6 8 6 10 5 51 50 5 51 16 21 11 8 14 5 8 6 8 7 3 17 18 19 2 + + + + + + + 19 8 22 mmed mstro rvthres lsource rlsource ldrain rldrain lgate rlgate 20 8 17 18 rft2p03l
?002 fairchild semiconductor corporation rft2p03l rev. b spice thermal model rev july 98 rft2p03l ctherm1 9 8 1.9e-5 ctherm2 8 7 3.0e-4 ctherm3 7 6 1.2e-3 ctherm4 6 5 3.5e-3 ctherm5 5 4 2.0e-2 ctherm6 4 3 6.5e-2 ctherm7 3 2 2.0e-1 ctherm8 2 1 1 rtherm1 9 8 3.5e-2 rtherm2 8 7 8.5e-2 rtherm3 7 6 3.5e-1 rtherm4 6 5 1.85 rtherm5 5 4 2.75 rtherm6 4 3 15 rtherm7 3 2 30 rtherm8 2 1 50 rtherm4 rtherm6 rtherm5 rtherm3 rtherm2 rtherm1 ctherm4 ctherm6 ctherm5 ctherm3 ctherm2 ctherm1 1 4 5 6 7 8 9 junction ambient 2 3 rtherm7 rtherm8 ctherm7 ctherm8 rft2p03l
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
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